1. Field of the invention
The present invention relates to a power on reset generating circuit and method thereof, more particularly to, a power on reset generating circuit and method thereof wherein said reset signal remains as a constant which is independent of power ascending or descending or repeated switching.
2. Description of the Prior Arts
The function of power on reset circuits is to provide a reset signal for each of individual ICs in the main circuit so as to ensure the IC to start functioning synchronously.
Refer to FIG. 1, a conventional reset signal generating circuit comprises a resistor 101, a capacitor 102, as well as a buffer 105. The buffer 105 comprises a Schmitt trigger 103 and an inverter 104. While the power is ascending, the power is charging said capacitor 102 via said resistor 101. At the time of voltage charging for the capacitor 102 to exceed the transient state point of Schmitt trigger 103 at the next stage, the circuit generates a reset signal. The reset voltage is usually relevant to the speed of power ascending. The faster the voltage of the power ascends, the higher the reset voltage is. The slower the voltage of the power ascends, the lower the reset voltage is or sometime there is no reset signal generated. During the process of voltage descending, due to the passive discharging mechanism as suggested by the conventional RC structure, the capacitor 102 in the circuit is discharging the power. As a result, during the power descending procedure, the voltage at the capacitor is higher than the power all the time, and no reset signal is generated accordingly. Another issue to be addressed is, after a plurality of reset signals being generated, the capacitor 102 cannot be fully discharged to ground, as depicted in FIG. 2. When the process of transient discharging followed consecutively by a power ascending, a higher power on reset voltage or a system failure to generate a reset signal may occur such that the system functions improperly.
Accordingly, in view of the above drawbacks, it is an imperative that an improved power on reset generating circuit is designed so as to solve the drawbacks as the foregoing.